加拿大华人论坛 加拿大生活信息opening：New Grad Mixed Signal DSP Engineer
在加拿大
email me your resume if seriously interested at [email protected]: New Grad Mixed Signal DSP Engineer - 1105830001About the Job:Position: DSP DesignerDivision: MSDG Location: Burnaby, BCThe Mixed-Signal Design Group (MSDG) provides IP to various business units within the company, with a current focus on DSP-based SERDES. These SERDES designs incorporate GHz-rate DSP blocks with adaptive equalization, timing recovery, and diagnostics. The DSP team (a sub-division of MSDG) is responsible for the design, verification, synthesis, and lab support of these blocks.The DSP team also works on designs that utilize Maximum Likelihood Estimation (MLE), Forward Error Correction (FEC), Fourier Transforms (FFTs/IFFTs), encoding/decoding, network timing, digital PLLs, and a variety of control loops like Automatic Gain Control (AGC), Automatic Frequency Control (AFC), etc.We are looking for a bright DSP designer for SERDES projects. There will opportunities to explore other areas too.Responsibilities:• Architectural definition, design, and implementation of hardware DSP blocks o Feasibility studies in Matlab/Simulink o RTL development in VHDL/Verilog o Block-level verification in Matlab/Verilog o Documentation, synthesis, back-end support• Support development from specification through to production by interacting with engineers in Validation, Applications, Product Development, Marketing and Production Engineering• Debug issues found in the company and customer labs• Represent company at conferences and customer eventsMandatory Qualifications: The minimum requirements for this job are:• Education: advanced degree in EE (BASc, MASc, or PhD)• A background in DSP design• Proficiency with Matlab and Simulink• The ability to work autonomously• Excellent written and oral communications skills• Ability to quickly ramp up on new technologiesOther Qualifications:The following qualifications are assets for the candidate, but not mandatory:• Experience with SERDES designs• Bit Error Rate (BER) estimation• Decision Feedback Equalizers (DFEs) and Feed Forward Equalizers (FFEs) design• Clock recovery loop design• Experience with all phases of digital design (specification, RTL coding, verification, synthesis, layout)• Experience with high speed timing (500MHz+)• Experience with power optimization of digital designs• Proficiency with C/C++• Worked on a product that has shipped in significant quantity• Comfort within the Unix/Linux O/S• Experience with customer interaction and support
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